#ifndef __ORION_H__
#define __ORION_H__

// declare an enumerated type that can be used to refer to interrupts by name, e.g. in calls to the NVIC configuration
// functions - the definitions here must match the vector table positions, offset so that IRQ0 (the 1st ASIC IRQ) has
// the value 0...
//
typedef enum IRQn
{
// Cortex-M0 core exceptions...
         NMI_IRQn = -14,
       Reset_IRQn = -15,
   HardFault_IRQn = -13,
         SVC_IRQn = -5,
      PendSV_IRQn = -2,
     SysTick_IRQn = -1,
// QIN-specific IRQs... (should match the vector defined in dig_qin_top.sv)
      Wakeup_IRQn = 0,
        GPIO_IRQn = 1,
    Brownout_IRQn = 2,
        VBAT_IRQn = 3,
   WatchdogA_IRQn = 4,
  LIN_Master_IRQn = 5,
   LIN_Slave_IRQn = 6,
        UART_IRQn = 7,
         ADC_IRQn = 8,
         PWM_IRQn = 9,
        Buck_IRQn = 10,
      Irq_11_IRQn = 11,
      Irq_12_IRQn = 12,
      Irq_13_IRQn = 13,
      Irq_14_IRQn = 14,
     Lullaby_IRQn = 15,
// Clough peripheral IRQs...
      Timer0_IRQn =  16,
      Timer1_IRQn =  17,
      Timer2_IRQn =  18,
   WatchdogM_IRQn =  19,
         BTE_IRQn =  20,
        SDIO_IRQn =  21
} IRQn_Type;
//
// and define a tell-tale macro that will prevent the clough.h header from attempting to re-define this with the
// default (non-ASIC-specific) version...
//
#define __IRQn_Type

#include <stdint.h>
#include <stdbool.h>
#include "rugby_sfr.h"
#include "verne.h"

// things that should be auto-generated in the SFR headers?

#define CLOCKSRC_HFCLKSEL_RC    0
#define CLOCKSRC_HFCLKSEL_XO    1
#define CLOCKSRC_SYSCLKSEL_LF   0
#define CLOCKSRC_SYSCLKSEL_HF   1

#define RESETCTRL_POR           1
#define RESETCTRL_BOR_3V3       2
#define RESETCTRL_BOR_2V6       4
#define RESETCTRL_BOR_1V8       8
#define RESETCTRL_WDTA          16

#define PMUA_CTRL_HIBERNATE     1
#define PMUA_CTRL_FASTBOOT      2
#define PMUA_CTRL_FASTSHUTDOWN  4

#endif


